We have planned to do Software Defined Radio by using FPGA. Firstly, we separated this project into two parts which are the transmitter part and receiver part. On the transmitter part we took sinusoidal wave data from MATLAB. By using these data, sinusoidal wave was implemented on FPGA board. As long as we have done this issue, araised cosine filter was created on FPGA by doing thesame process. Then, we made raised cosine filter arrays with data that was expected to come from themicrophone, but we created data by hand, we could not use microphone.
After that we multiplied Sinusoidal wave and raised cosine filter arrays. As final process for transmitter part we added these arrays each other and observed transmitting wave form by using an oscilloscope. On the receiver part, we could not do so much thing but sinusoidal wave and raised cosine filter are used in this part. We will make Phase-Locked Loop for catching transmitting signal correctly.
Objectives
Generally, analog radios have one modulation type and they can not be implemented new technology easily. It is necessary to change their hardware to adjust modulation type. Because of that, people who use these radios have to pay money to change. In addition, analog radios’ transmitters are very expensive and large. We solve these problems by implementing software define radio on FPGA. We have chosen FPGA since it works faster than other microcontroller thanks to working parallel processing.
With this project, we want to create new platform for communication. This platform will work all digitally, and it can be implemented new technology easily. For example, if new modulation type, that is faster than other modulation types, is made, we can change code and keep using software defined radio.
Another usage area is that you can broadcast by using software define radio which is made by us. This broadcast will be more safety then analog systems. Because of that, communication between planes, ships or any other means of transport is provided by SDR.
Features and Specifications
Basically, sinusoidal signals and raised cosine filter are implemented on FPGA. We have implemented 4 QAM. In this method, data is separated two parts as imaginal and real. We have 8 bits data and this data is divided by twos. Four bits goes to one ROM and these represent imaginal part, other four bits goes to different ROM and these represent real part. These ROM are shown in Figure1. Raise cosine filter phase changes by data. If data bit is equal to 1, raised cosine is normal without any phase changing. If data bit is equal to 0 (normally it is equal to -1 but we chose like because it is easier), raised cosine is reverse with 180-degree phase changing. This raised cosine goes to their address (it is indicated figure 1). Finally, they are added each other and go to antenna.
